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TopLevel_DualPort_Ram_XilinxCore
- Top Level Dual Port Ram Core Project, VHDL code
project1_report1
- The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUs which share an address space. The processors share a second lev
OFDM
- 毕业论文(单片机类)毕业设计(论文)OFDM通信系统基带数据-Thesis (Singlechip category) Graduation Project (Thesis) OFDM base-band data communication system
FreeDCT-L
- Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
dct
- Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
dct-thesis
- Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
dct2
- Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
project
- synthesizable code for shift register of user defined size
VHDL
- 电子密码锁设计，可以改为其他原理相似的设计，比如和汽车安全系统相关的毕业设计-The design of electronic locks can be replaced by other theories of similar design, and automotive safety systems such as the graduation project related
tetris
- Our project is to design and implement a Tetris game by using FPGA. Tetris a puzzle game that uses 4 square blocks joining edge to edge to form various combinations of shapes. There are 7 unique shapes. The shapes are controlled with the arrow keys f
vhdl_main
- VHDL main project for impementing FFT algorithm
VHDL_fire_alarm_detection
- vhdl source code of fire detection system/fire alarm system especially for high rise building? This among the requirement :- according to my "fire detection system for tall building" project by using Spartan 3E FPGA, the vhdl program need
RS422
- 描述了有关RS422的标准及通信协议，便于开发者的项目开发-A descr iption of the RS422 standard and communications protocol to facilitate the developer s project development
79419150Zigbee-WSN
- zigbee file for project
registrorotador
- it s a register rotate vhdl project for xilinx
Assignment-3
- Assignment 3 Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. (1) Synthesize and (2) simulate these models respectively in the environment of Xilinx I
vhdl
- VHDL code project simulation
VHDL
- Project manager is reak vhdl old man
Simulation vhdl
- Verilog simulations of different project problems.
vlsi list
- project titles for btech ece